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DEFAULT.MAC
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1990-06-25
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2KB
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69 lines
*--- DEFAULT MACRO FILE for SHAREWARE version of LSYSTEM V S2.0
* 2/7/1990
*--- This is an example of an LSYSTEM INCLUDE file.
*
.MACRO 74LS20 1A 1B 1C 1D 1Y 2Y 2A 2B 2C 2D
*
* DUAL 4 input NAND gates.
*
LS20_1 1A 1B 1C 1D 1Y NAND4 (rise=9 fall=10)
LS20_2 2A 2B 2C 2D 2Y NAND4 (rise=9 fall=10)
.ENDM
*
.MACRO 74LS73 1CK 1CLR 1K 2CK 2CLK 2J 2QN 2Q 2K 1Q 1QN 1J
*
* DUAL JK flip-flops with CLEAR -- NE triggered.
*
LS73_1 1CK 1CKN INV (delay=1)
LS73_2 2CK 2CKN INV (delay=1)
LS73_3 1CKN 1CLR 1J 1K 1Q 1QN JKFF_C_PE (rise=11 fall=15)
LS73_4 2CKN 2CLR 2J 2K 2Q 2QN JKFF_C_PE (rise=11 fall=15)
.ENDM
.MACRO 74LS75 1NQ 1D 2D E3_4 3D 4D 4NQ 4Q 3Q 3NQ E1_2 2NQ 2Q 1Q
*
* QUAD 4-BIT BISTABLE LATCH
*
GA1 E1_2 75A1 INV (RISE=4 FALL=5)
GB1 E1_2 1D 75B1 AND2 (RISE=3 FALL=5)
GC1 75A1 1Q 75C1 AND2 (RISE=3 FALL=5)
GD1 75B1 75C1 1NQ NOR2 (RISE=5 FALL=5)
GE1 1NQ 1Q INV (RISE=4 FALL=5)
*
GA2 E1_2 75A2 INV (RISE=4 FALL=5)
GB2 E1_2 2D 75B2 AND2 (RISE=3 FALL=5)
GC2 75A2 2Q 75C2 AND2 (RISE=3 FALL=5)
GD2 75B2 75C2 2NQ NOR2 (RISE=5 FALL=5)
GE2 2NQ 2Q INV (RISE=4 FALL=5)
*
GA3 E3_4 75A3 INV (RISE=4 FALL=5)
GB3 E3_4 3D 75B3 AND2 (RISE=3 FALL=5)
GC3 75A3 3Q 75C3 AND2 (RISE=3 FALL=5)
GD3 75B3 75C3 3NQ NOR2 (RISE=5 FALL=5)
GE3 3NQ 3Q INV (RISE=4 FALL=5)
*
GA4 E3_4 75A4 INV (RISE=4 FALL=5)
GB4 E3_4 4D 75B4 AND2 (RISE=3 FALL=5)
GC4 75A4 4Q 75C4 AND2 (RISE=3 FALL=5)
GD4 75B4 75C4 4NQ NOR2 (RISE=5 FALL=5)
GE4 4NQ 4Q INV (RISE=4 FALL=5)
*
.ENDM
*-- NON RETRIGGARABLE 2000 nS monostable. [eg. el IN OUT mono2000]
*-- A rising edge on pulse input IN will cause OUTPUT to switch HIGH for 2000nS
.macro MONO2000 in out
elc in t3 t1 AND2 (delay = 1)
elc t1 t2 inv (delay = 1)
elc t2 out inv (rise = 1 FALL = 1997)
elc out t3 inv (delay = 1)
.endm